Different types of integrated circuit devices may have programmable resources. While an application specific integrated circuit (ASIC) having programmable resources, other devices comprise dedicated programmable logic devices (PLDs). One type of PLD is the Complex Programmable Logic Device (CPLD). A CPLD includes two or more function blocks that are connected together and to input/output (I/O) resources by an interconnect switch matrix, and may include a two-level AND/OR structure similar to that used in a Programmable Logic Array (PLA) or a Programmable Array Logic (PAL) device. Another type of PLD is a field programmable gate array (FPGA). In a typical FPGA, an array of configurable logic blocks (CLBs) is coupled to programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a hierarchy of programmable routing resources. These CLBs, IOBs, and programmable routing resources are customized by loading a configuration bitstream into configuration memory cells of the FPGA. For both of these types of programmable logic devices, the functionality of the device is controlled by configuration data bits of a configuration bitstream (or configuration data bits sent during a partial reconfiguration) provided to the device for that purpose.
Many PLDs enable reconfiguration and have used an infrastructure for control of independent reconfigurable elements that consists of “Global” control signals, i.e., signals which are broadcast from a central controller, along with local state elements which can mask the effect of these Global controls, often referred to as Global Signal Control (GSC) bits. The GSC bit infrastructure depends on software which can keep track of the state of every GSC bit on a device. This can be described as a “Global Snapshot” of GSC bit state. Any partial reconfiguration event in the system requires the software to have a Global Snapshot of device programming before and after, as well as knowledge of the state of all the GSC bits on the device. There can be tens of thousands of independent functional blocks and GSC bits on a large reconfigurable device. As a result, the software needed to generate the programming and control information is very large and memory/compute intensive. This type of software often requires hours to run on a powerful computer.
Therefore, there is a need for circuits for and methods of configuring and reconfiguring integrated circuit devices that overcome problems of conventional devices.